`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:06:55 09/13/2011 
// Design Name: 
// Module Name:    IOControlFSM 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module IOControlFSM(Master_clk, reset, instruction, op, buffers);

input Master_clk;
input reset;
input [15:0] instruction;
output [7:0] op;
output [4:0] buffers;

int state;
parameter FETCH=2'b00;
parameter DECODE=2'b01;
parameter EXECUTE=2'b10;
parameter STOR = 2'b11;

always @(posedge Master_clk, posedge reset)begin

	if(reset)begin
		state = 00;
	end
		state = instruction;

end

always @(posedge Master_clk) begin

	case(state)
	
		FETCH:


		DECODE:

	
	endcase

end

endmodule
